The 74FCT810T is a dual bank inverting/ non-inverting clock driver built using advanced dual metal CMOS technology. It consists of two banks of drivers, one inverting and one non-inverting. Each bank drives five output buffers from a standard TTL-compatible input. The FCT810T has low output skew, pulse skew and package skew. Inputs are designed with hysteresis circuitry for improved noise immunity. The outputs are designed with TTL output levels and controlled edge rates to reduce signal noise. The part has multiple grounds, minimizing the effects of ground inductance.

Features

  • 0.5 MICRON CMOS Technology
  • Guaranteed low skew < 600ps (max.)
  • Very low duty cycle distortion < 700ps (max.)
  • Low CMOS levels
  • TTL compatible inputs and outputs
  • TTL level output voltage swings
  • High drive: -32mA IOH, +48mA IOL
  • Two independent output banks with 3-state control: – One 1:5 inverting bank – One 1:5 non-inverting bank
  • Available in QSOP, SSOP, and SOIC packages

Product Options

注文可能な製品ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
74FCT810CTPYG Obsolete PYG20 SSOP 20 C Yes Tube
Availability
74FCT810CTQG Obsolete PCG20 QSOP 20 C Yes Tube
Availability
74FCT810CTSOG Obsolete PSG20 SOIC 20 C Yes Tube
Availability

技術資料

タイトル 他の言語 タイプ 形式 サイズ 日付
アプリケーションノート、ホワイトペーパー
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-845 Termination - LVCMOS Application Note PDF 62 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
その他資料
IDT Clock Distribution Overview (日本語) English Overview PDF 3.79 MB