The 82P33714 Synchronous Equipment Timing Source (SETS) for Synchronous Ethernet (SyncE) provides tools to manage timing references, clock generation and timing paths for SyncE based clocks, per ITU-T G.8264 and ITU-T G.8262. 82P33714 meets the requirements of ITU-T G.8262 for synchronous Ethernet Equipment Clocks (EECs) and ITU-T G.813 for Synchronous Equipment Clocks (SEC). The device outputs low-jitter clocks that can directly synchronize Ethernet interfaces; as well as SONET/SDH and PDH interfaces. For 10G-40G SyncE single-board applications, see the 82P33731

IDT’s third generation Universal Frequency Translator family also includes the 8T49N285 (2-in / 1-PLL / 8-out), 8T49N286 (4-in / 2-PLL / 8-out), and 8T49N287 (2-in / 2-PLL / 8-out), and the 8T49N242 (2-in / 1-PLL / 4-out).

► Download the Altera and IDT Synchronous Ethernet Solution for ITU-T G.8262 white paper

Features

  • Complies with ITU-T G.8262 for Synchronous Ethernet Equipment Clock (EEC), and G.813 for Synchronous Equipment Clock (SEC), and Telcordia GR-253-CORE for Stratum 3 and SONET Minimum Clock (SMC)
  • DPLLs lock to a wide range of reference clock frequencies including: 10/100/1000 Ethernet, 10G Ethernet, OTN, SONET/SDH, PDH, TDM, GSM, CPRI/OBSAI and GNSS frequencies using fractional-N input dividers
  • Generates clocks for: Ethernet, SONET/SDH and PDH interfaces: jitter generation <1 ps RMS (12 kHz to 20 MHz)
  • Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables, revertive and non-revertive settings and other programmable settings
  • Prevents output frequency corruption due to a bad PHY reference by accepting Loss of Signal (LOS) inputs from PHYs that immediately disqualify a reference
  • DPLL1 can be configured as a DCO (Digitally Controlled Oscillator) to support IEEE 1588 based clock generation under external processor control
  • Supports network timing master applications by locking to 1 PPS (Pulse Per Second) references from GPS or other GNSS sources
  • Eases local oscillator sourcing by supporting any of eight common TCXO/OCXO frequencies for the System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz, 24.576 MHz, 25 MHz or 30.72 MHz
  • Automatically loads configuration from an external EPROM after reset without processor intervention
  • 72 pin QFN package

Product Options

注文可能な製品ID Part Status Pkg. Code Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
82P33714ANLG Active NLG72P2 C Yes Tray
Availability
82P33714ANLG8 Active NLG72P2 C Yes Reel
Availability

技術資料

タイトル 他の言語 タイプ 形式 サイズ 日付
データシート
82P33714 Datasheet Datasheet PDF 1.04 MB
アプリケーションノート、ホワイトペーパー
AN-890 SETS for IEEE 1588 and Synchronous Ethernet 82P337xx Register Map Application Note PDF 582 KB
AN-950 82P338XX/9XX Usage of a SYNC Input for Clock Alignment Application Note PDF 175 KB
AN-861 Recommended Crystals for IDT VCXO-based Synchronization PLLs Application Note PDF 214 KB
AN-807 Recommended Crystal Oscillators for NetSynchro WAN PLL Application Note PDF 77 KB
AN-946 Using a 19.2MHz System Clock with 82P337xx/8xx/9xx Application Note PDF 165 KB
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-901 How to Implement Master/Slave for SETS and SMU Devices on Timing Redundancy Designs Application Note PDF 475 KB
AN-865 8T49N285_6_7 Frequency Synchronization Compliance Report Application Note PDF 1.04 MB
ITU-T Profiles for IEEE 1588 White Paper PDF 1.17 MB
AN-893 8T49N241_2 Frequency Synchronization Compliance Report Application Note PDF 1.02 MB
AN-871 Generating SyncE Line Cards Using IDT UFT3G Application Note PDF 688 KB
AN-846 Termination - LVDS Application Note PDF 50 KB
AN-845 Termination - LVCMOS Application Note PDF 62 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-839 RMS Phase Jitter Application Note PDF 149 KB
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 32 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
AN-801 Crystal-High Drive Level Application Note PDF 109 KB
AN-806 Power Supply Noise Rejection Application Note PDF 353 KB
PCN / PDN
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location Product Change Notice PDF 583 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB
PCN# : N1412-01 Die revision change 82P33814, 82P33831, 82P33714, 82P33731, 82P33810 Product Change Notice PDF 40 KB
その他資料
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Products for Wired Broadband Applications Application Briefs PDF 686 KB
IDT Clock Generation Overview (日本語) English Overview PDF 1.83 MB
IDT Clock Distribution Overview (日本語) English Overview PDF 3.79 MB
Timing Fabric for Communications Equipment Overview Overview PDF 263 KB

ソフトウェア/ツール

タイトル 他の言語 タイプ 形式 サイズ 日付
Timing Commander Installer (v1.13.1.21509) Software ZIP 20.40 MB
82P33xx4 Timing Commander Personality Software TCP 3.50 MB
82P33714NLG BSDL Model - BSDL BSD 15 KB
82P33714A IBIS Model Model - IBIS ZIP 173 KB

Evaluation Boards

Part Number Title 昇順で並び替え
82EBP33814 Evaluation Board for 82P33814 Synchronization Management Unit for IEEE 1588 and Synchronous Ethernet