The 8V31012 is a 1-to-12 Differential HCSL Fanout Buffer. The 8V31012 is designed to translate any differential signal levels to differential HCSL output levels. An external reference resistor is used to set the value of the current supplied to an external load/termination resistor. The load resistor value is chosen to equal the value of the characteristic line impedance of 50Ω. The 8V31012 is characterized at an operating supply voltage of 3.3V. 

The differential HCSL outputs, accurate crossover voltage and duty cycle make the 8V31012 ideal for interfacing to PCI Express and FBDIMM applications.

Features

  • Twelve differential HCSL outputs
  • Translates any differential input signal (LVPECL, LVHSTL, LVDS, HCSL) to HCSL levels without external bias networks
  • Maximum output frequency: 250MHz
  • Output skew: 265ps (typical)
  • VOH: 850mV (maximum)
  • Full 3.3V supply voltage
  • Available in lead-free (RoHS 6) package
  • -40°C to 85°C ambient operating temperature

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
8V31012NLGI Active NLG48P1 VFQFPN 48 I Yes Tray
Availability
8V31012NLGI8 Active NLG48P1 VFQFPN 48 I Yes Reel
Availability

技術資料

タイトル 他の言語 タイプ フォーマット ファイルサイズ 日付
データシート
8V31012 Final Data Sheet Datasheet PDF 449 KB 10月 26, 2015
アプリケーションノート、ホワイトペーパー
AN-828 Termination - LVPECL Application Note PDF 229 KB 7月 5, 2016
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB 5月 12, 2014
AN-843 PCI Express Reference Clock Requirements Application Note PDF 1.81 MB 5月 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB 5月 11, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB 5月 10, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB 5月 7, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB 5月 5, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB 5月 5, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB 5月 5, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB 4月 23, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB 4月 23, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB 1月 14, 2014
PCN / PDN
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location Product Change Notice PDF 583 KB 12月 19, 2016
その他資料
Timing Solutions Products Overview Overview PDF 4.11 MB 10月 31, 2018
PCI Express® Timing Solutions Overview Overview PDF 301 KB 4月 19, 2018
IDT Clock Generation Overview (日本語) English Overview PDF 1.83 MB 4月 28, 2016
IDT Clock Distribution Overview (日本語) English Overview PDF 3.79 MB 4月 24, 2016
IDT Fanout Buffers Product Overview Product Brief PDF 739 KB 2月 16, 2015
High-Performance, Low-Phase Noise Clocks Buffers product brief Product Brief PDF 378 KB 8月 13, 2012