The 9DB1933 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB1933 is driven by a differential SRC output pair from an IDT 932S421, 932SQ420, or equivalent, main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking.

Features

  • 19 - 0.7 V current mode differential HCSL output pairs
  • 8 Selectable SMBus Addresses/Mulitple devices can share the same SMBus Segment
  • 11 dedicated and 3 group OE# pins/Hardware control of the outputs
  • PLL or bypass mode/PLL can dejitter incoming clock
  • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's
  • Spread spectrum compatible, tracks spreading input clock for low EMI
  • SMBus Interface, unused outputs can be disabled
  • Supports undriven differential outputs in Power Down mode for power management
  • Cycle-to-cycle jitter <50 ps
  • Output-to-output skew < 150 ps
  • PCIe Gen3 phase jitter < 1.0 ps RMS

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
9DB1933AKLF Active NLG72P1 VFQFPN 72 C Yes Tray
Availability
9DB1933AKLFT Active NLG72P1 VFQFPN 72 C Yes Reel
Availability

技術資料

タイトル 他の言語 タイプ フォーマット ファイルサイズ 日付
データシート
9DB1933 Datasheet Datasheet PDF 185 KB 12月 5, 2011
9DB1933 Datasheet Datasheet PDF 185 KB 11月 15, 2011
アプリケーションノート、ホワイトペーパー
AN-828 Termination - LVPECL Application Note PDF 229 KB 7月 5, 2016
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB 5月 12, 2014
AN-843 PCI Express Reference Clock Requirements Application Note PDF 1.81 MB 5月 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB 5月 11, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB 5月 10, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB 5月 7, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB 5月 5, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB 4月 23, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB 4月 23, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB 1月 14, 2014
PCN / PDN
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location Product Change Notice PDF 583 KB 12月 19, 2016
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB 1月 27, 2016
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB 11月 12, 2015
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 95 KB 10月 21, 2015
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 50 KB 7月 20, 2015
PCN# : A1311-03R1 Alternate Assembly Locations Product Change Notice PDF 43 KB 2月 15, 2014
PCN# : A1311-03 Alternate Assembly Locations Product Change Notice PDF 140 KB 12月 2, 2013
PCN# : A1308-01 Add ASEK as Alternate Assembly for VFQFPN-72 Product Change Notice PDF 103 KB 8月 17, 2013
その他資料
Timing Solutions Products Overview Overview PDF 4.11 MB 10月 31, 2018
PCI Express® Timing Solutions Overview Overview PDF 301 KB 4月 19, 2018
IDT Clock Generation Overview (日本語) English Overview PDF 1.83 MB 4月 28, 2016
IDT Clock Distribution Overview (日本語) English Overview PDF 3.79 MB 4月 24, 2016
IDT Fanout Buffers Product Overview Product Brief PDF 739 KB 2月 16, 2015
High-Performance, Low-Phase Noise Clocks Buffers product brief Product Brief PDF 378 KB 8月 13, 2012