NOTICE - The following device(s) are recommended alternatives:
The 9FGL839 is an 8 output differential synthesizer for PCI Express Gen1, Gen2, and Gen3 applications. It has integrated terminations providing direction connection to 100 ohm transmission lines and saving 32 resistors compared to standard HCSL outputs. The 9FGL839 supports Common, Data and Separate Reference no-Spread (SRnS) PCIe clock architectures.

Features

  • Integrated terminations; save 32 resistors compared to standard HCSL outputs
  • LP-HCSL outputs; support separate VDDIO rail and 130mW typical power consumption
  • 8 OE# pins; Hardware control of each output
  • 25 MHz crystal input; exact synthesis
  • 100 MHz operation; supports PCIe and SATA applications
  • VDDIO; allows outputs to run from lower voltage rail to save power
  • OE# pins have 1.5V high input threshold; direct interface to 1.8-3.3 V systems
  • <130 mW power consumption (typical)
  • Cycle-to-cycle jitter <50 ps
  • Output-to-output skew <100 ps
  • PCIe Gen2 phase jitter <3.0 ps RMS
  • PCIe Gen3 phase jitter <1.0 ps RMS
  • PCIe Gen3 SRnS clock phase jitter <0.7 ps RMS

Product Options

注文可能な製品ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
9FGL839AKILF Obsolete NDG48P2 VFQFPN 48 I Yes Tray
Availability
9FGL839AKILFT Obsolete NDG48P2 VFQFPN 48 I Yes Reel
Availability
9FGL839AKLF Obsolete NDG48P2 VFQFPN 48 C Yes Tray
Availability
9FGL839AKLFT Obsolete NDG48P2 VFQFPN 48 C Yes Reel
Availability

技術資料

タイトル 他の言語 タイプ 形式 サイズ 日付
データシート
9FGL839 Datasheet Datasheet PDF 158 KB
アプリケーションノート、ホワイトペーパー
AN-918 Programmable Clocks vs Crystal Oscillators Application Note PDF 221 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT's "Universal" Low-Power HCSL Outputs Application Note PDF 354 KB
AN-879 Low-Power HCSL vs Traditional HCSL Application Note PDF 150 KB
AN-843 PCI Express Reference Clock Requirements Application Note PDF 1.81 MB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-839 RMS Phase Jitter Application Note PDF 149 KB
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 32 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 52 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
AN-808 PCI Express/HCSL Termination Application Note PDF 54 KB
PCN / PDN
PDN# : CQ-17-04(R1) Product Discontinuance Notice Product Discontinuation Notice PDF 606 KB
PDN# : CQ-17-04 Product Discontinuance Notice Product Discontinuation Notice PDF 599 KB
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location Product Change Notice PDF 583 KB
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 95 KB
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 50 KB
PCN# : A1208-01R1 Gold to Copper Wire Product Change Notice PDF 254 KB
その他資料
PCI Express Timing Solutions Overview Overview PDF 275 KB
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview (日本語) English Overview PDF 1.83 MB
IDT Clock Distribution Overview (日本語) English Overview PDF 3.79 MB