The 9QXL2001 is a 20-output very-low-additive phase jitter fanout buffer for PCIe Gen4, Gen5 and UPI applications. The 9QXL2001 provides two methods to control output enables; standard OE# pins and SMBus enable bits, or a simple 3-wire serial interface that is independent of the SMBus. The OE Control Mode is set via a hardware strap. It offers integrated terminations for 85Ω transmission lines.
 

Features

  • Traditional 8 OE# pins allow hardware control of 8 outputs and 20 SMBus bits allow software control of each output
  • Simple 3-wire Side-Band Interface allows real-time control of all 20 outputs in real time
  • Outputs remain Low/Low when powered up with floating input clock
  • Low-Power HCSL (LP-HCSL) outputs reduce device power consumption by 50%
  • Zo = 85Ω outputs eliminate 80 resistors, saving 130mm2 of area
  • 9 selectable SMBus addresses
  • Spread spectrum compatible
  • 6 × 6 mm dual-row 80-GQFN

Product Options

注文可能な製品ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
9QXL2001BNHGI Active NHG80P1 VFQFPN 80 I Yes Tray
Availability
9QXL2001BNHGI8 Active NHG80P1 VFQFPN 80 I Yes Reel
Availability

技術資料

タイトル 他の言語 タイプ 形式 サイズ 日付
データシート
9QXL2001B Datasheet Datasheet PDF 421 KB
アプリケーションノート、ホワイトペーパー
AN-1001 Combining PhiClock™ and 9ZXL1951D for PCIe Gen4/5 Application Note PDF 103 KB
AN-975 Cascading PLLs Application Note PDF 128 KB
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT's "Universal" Low-Power HCSL Outputs Application Note PDF 354 KB
AN-879 Low-Power HCSL vs Traditional HCSL Application Note PDF 150 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
AN-808 PCI Express/HCSL Termination Application Note PDF 54 KB
その他資料
Timing Solutions Products Overview Overview PDF 4.11 MB
PCI Express® Timing Solutions Overview Overview PDF 301 KB
IDT Clock Generation Overview (日本語) English Overview PDF 1.83 MB
IDT Clock Distribution Overview (日本語) English Overview PDF 3.79 MB