The IDT8SLVD1208-33I is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The IDT8SLVD1208-33I is characterized to operate from a 3.3V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the IDT8SLVD1208-33I ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and eight low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.
 
For a 2.5 V version of this device, please refer to the 8SLVD1208I

Features

  • Eight low skew, low additive jitter LVDS output pairs
  • Two selectable, differential clock input pairs
  • Differential PCLK, nPCLK pairs can accept the following differential input levels: LVDS, LVPECL
  • Maximum input clock frequency: 2GHz (maximum)
  • LVCMOS/LVTTL interface levels for the control select input
  • Output skew: 8ps (typical)
  • Propagation delay: 240ps (typical)
  • Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V, 10kHz - 20MHz: 82fs (typical)
  • Maximum device current consumption (IDD): 190mA (maximum) @ 3.465V
  • 3.3V supply voltage
  • Lead-free (RoHS 6), 28-Lead VFQFN package
  • -40°C to 85°C ambient operating temperature

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
8SLVD1208-33NBGI Active NBG28 VFQFPN 28 I Yes Tray
Availability
8SLVD1208-33NBGI8 Active NBG28 VFQFPN 28 I Yes Reel
Availability

技術資料

タイトル 他の言語 タイプ フォーマット ファイルサイズ 日付
データシート
IDT8SLVD1208-33I Datasheet Datasheet PDF 394 KB 2月 11, 2014
アプリケーションノート、ホワイトペーパー
AN-846 Termination - LVDS Application Note PDF 50 KB 5月 12, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB 5月 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB 5月 11, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB 5月 7, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB 5月 5, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB 5月 5, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB 5月 5, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB 4月 23, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB 4月 23, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB 1月 14, 2014
PCN / PDN
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location Product Change Notice PDF 583 KB 12月 19, 2016
その他資料
Timing Solutions Products Overview Overview PDF 4.11 MB 10月 31, 2018
RF Timing Family Product Overview Overview PDF 723 KB 10月 24, 2018
IDT Clock Generation Overview (日本語) English Overview PDF 1.83 MB 4月 28, 2016
IDT Clock Distribution Overview (日本語) English Overview PDF 3.79 MB 4月 24, 2016
IDT Fanout Buffers Product Overview Product Brief PDF 739 KB 2月 16, 2015
High-Performance, Low-Phase Noise Clocks Buffers product brief Product Brief PDF 378 KB 8月 13, 2012
ソフトウェア/ツール
8SLVD1208-33I IBIS Model Model - IBIS ZIP 35 KB 10月 20, 2015

ソフトウェア/ツール

タイトル 他の言語 タイプ フォーマット ファイルサイズ 日付
8SLVD1208-33I IBIS Model Model - IBIS ZIP 35 KB 10月 20, 2015