The 8V19N491-36 is a fully integrated FemtoClock® NG jitter attenuator and clock synthesizer. The device is designed as a high-performance clock solution for conditioning and frequency/phase management of wireless base station radio equipment boards. The device is optimized to deliver excellent phase noise performance as required in GSM, WCDMA, LTE, and LTE-A radio board implementations. The device supports JESD204B subclass 0 and 1 clocks. A two-stage PLL architecture supports both jitter attenuation and frequency multiplication. The first stage PLL is the jitter attenuator and uses an external VCXO for best possible phase noise characteristics. The second stage PLL locks on the VCXO-PLL output signal and synthesizes the target frequency.

The 8V19N491-36 supports the clock generation of high-frequency clocks from the selected VCO and low-frequency synchronization signals (SYSREF). SYSREF signals are internally synchronized to the clock signals. Delay functions exist for achieving alignment and controlled phase delay between system reference and clock signals and to align/delay individual output signals. The four redundant inputs are monitored for activity. Four selectable clock switching modes are provided to handle clock input failure scenarios. Auto-lock, individually programmable output frequency dividers, and phase adjustment capabilities are added for flexibility. The device is configured through a 3/4-wire SPI interface and reports lock and signal loss status in internal registers and via a lock detect (LOCK) output. Internal status bit changes can also be reported via the nINT output. The 8V19N491-36 is ideal for driving converter circuits in wireless infrastructure, radar/imaging, and instrumentation/medical applications.

For information regarding evaluation boards and material, please contact your local IDT sales representative.

Features

  • High-performance clock RF-PLL with support for JESD204B
  • Optimized for low phase noise: -152.5dBc/Hz (800kHz offset; 245.76MHz clock)
  • Integrated phase noise of 65fs RMS typical (12kHz–20MHz) at 737.28MHz
  • Dual-PLL architecture
  • First PLL stage with external VCXO for clock jitter attenuation
  • Second PLL with internal FemtoClock NG PLL: 3686.4MHz
  • Five output channels with a total of 18 outputs
  • Configurable integer clock frequency dividers
  • Supported clock output frequencies include: 3686.4, 1843.2, 1228.8, 737.28, 614.4, 368.4, 307.2, 245.76, 153.6, 122.88 and 61.44 MHz
  • Low-power LVPECL/LVDS outputs support configurable signal amplitude
  • Phase delay circuits
  • Redundant input clock architecture with four inputs including input activity monitoring and switching
  • SYSREF generation modes include internal and external trigger mode for JESD204B
  • Supply voltage: 3.3V
  • SPI Interface, 3/4 wire configurable
  • Package: 11 × 11 mm, 100-CABGA
  • Temperature range: -40°C to +85°C

Product Options

注文可能な製品ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
8V19N491-36BDGI Active BDG100D1 CABGA 100 I Yes Tray
Availability
8V19N491-36BDGI8 Active BDG100D1 CABGA 100 I Yes Reel
Availability

技術資料

タイトル 他の言語 タイプ 形式 サイズ 日付
データシート
8V19N491-36 Datasheet Datasheet PDF 1.02 MB
ユーザーガイド
8V19N49x Hardware Design Guide Guide PDF 570 KB
アプリケーションノート、ホワイトペーパー
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-839 RMS Phase Jitter Application Note PDF 149 KB
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 32 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
AN-806 Power Supply Noise Rejection Application Note PDF 353 KB
その他資料
Timing Solutions Products Overview Overview PDF 4.11 MB
RF Timing Family Product Overview Overview PDF 723 KB
8V19N49x RF Sampling Clocks with Jitter Attenuation Overview Overview PDF 1.21 MB
IDT Products for Radio Applications (日本語) English Product Brief PDF 2.34 MB
IDT Clock Generation Overview (日本語) English Overview PDF 1.83 MB
IDT Clock Distribution Overview (日本語) English Overview PDF 3.79 MB
RF-Grade Clock Jitter Attenuator and Frequency Synthesizer Product Brief Product Brief PDF 847 KB

ソフトウェア/ツール

タイトル 他の言語 タイプ 形式 サイズ 日付
8V19N480-490 Timing Commander Personality File (v5.0.1) Software ZIP 4.36 MB
8V19N491-36 IBIS Model Model - IBIS ZIP 270 KB