The 853S9252I is a 2.5V/3.3V ECL/LVPECL fanout buffer designed for high-speed, low phase-noise wireless infrastructure applications. The device fanouts a differential input signal to two ECL/LVPECL outputs. Optimized for low additive phase-noise, sub-100ps output rise and fall times, low output skew and high-frequencies, the 853S9252I is an effective solution for high-performance clock and data distribution applications, for instance driving the reference clock inputs of ADC/DAC circuits. Internal input termination, a bias voltage output (VREF) for AC-coupling and small packaging (3.0mm x 3.0mm 16-lead VFQFN) supports space-efficient board designs. The 853S9252I operates from a full 2.5V or 3.3V power supply and supports the industrial temperature range of -40°C to 85°C. The extended temperature range also supports wireless infrastructure, tele-communication and networking end equipment requirements.

Features

  • 1:2 differential clock/data fanout buffer
  • Clock frequency: 3GHz (maximum)
  • Two differential 2.5V/3.3V ECL/LVPECL clock output
  • Differential input accepts ECL/LVPECL, LVDS and CML levels
  • Additive phase jitter, RMS @ 122.88MHz: 45fs (typical)
  • Propagation delay: 175ps (maximum), VCC = 3.3V
  • Output rise/fall time: 135ps (maximum), VCC = 3.3V
  • Internal input signal termination
  • Supply voltage: 2.5V-5% to 3.3V+10%
  • Available in Lead-free (RoHS 6) package
  • -40°C to 85°C ambient operating temperature

Product Options

注文可能な製品ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
853S9252BKILF Active NLG16P2 VFQFPN 16 I Yes Tube
Availability
853S9252BKILFT Active NLG16P2 VFQFPN 16 I Yes Reel
Availability

技術資料

タイトル 他の言語 タイプ 形式 サイズ 日付
データシート
ICS853S9252I Datasheet Datasheet PDF 396 KB
アプリケーションノート、ホワイトペーパー
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
PCN / PDN
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility Product Change Notice PDF 983 KB
PCN# : A1807-01 Gold wire to Copper Wire Product Change Notice PDF 32 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB
PCN# : A1403-03 Gold wire to Copper wire Product Change Notice PDF 42 KB
その他資料
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Products for Radio Applications (日本語) English Product Brief PDF 2.34 MB
IDT Clock Generation Overview (日本語) English Overview PDF 1.83 MB
IDT Clock Distribution Overview (日本語) English Overview PDF 3.79 MB