The 87016 is a low skew, 1:16 LVCMOS/LVTTL Clock Generator. The device has 4 banks of 4 outputs and each bank can be independently selected for ÷1 or ÷2 frequency operation. Each bank also has its own power supply pins so that the banks can operate at the following different voltage levels: 3.3V, 2.5V, and 1.8V. The low impedance LVCMOS/ LVTTL outputs are designed to drive 50? series or parallel terminated transmission lines. The divide select inputs, DIV_SELA:DIV_SELD, control the output frequency of each bank. The output banks can be independently selected for ÷1 or ÷2 operation. The bank enable inputs, CLK_ENA:CLK_END, support enabling and disabling each bank of outputs individually. The CLK_ENA:CLK_END circuitry has a synchronizer to prevent runt pulses when enabling or disabling the clock outputs. The master reset input, nMR/OE, resets the ÷1/÷2 flip flops and also controls the active and high impedance states of all outputs. This pin has an internal pull-up resistor and is normally used only for test purposes or in systems which use low power modes. The 87016 is characterized to operate with the core at 3.3V and the banks at 3.3V, 2.5V, or 1.8V. Guaranteed bank, output, and part-to-part skew characteristics make the 87016 ideal for those clock applications demanding well-defined performance and repeatability.


  • Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs)
  • Selectable differential CLK1, nCLK1 or LVCMOS clock input
  • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
  • CLK0 supports the following input types: LVCMOS, LVTTL
  • Maximum output frequency: 250MHz
  • Independent bank control for ÷1 or ÷2 operation
  • Independent output bank voltage settings for 3.3V, 2.5V, or 1.8V operation
  • Asynchronous clock enable/disable
  • Output skew: 170ps (maximum)
  • Bank skew: 30ps (maximum)
  • Part-to-part skew: 750ps (maximum)
  • 3.3V core, 3.3V, 2.5V, or 1.8V output operating supply
  • 0°C to 85°C ambient operating temperature
  • Available in lead-free RoHS compliant package

Product Options

注文可能な製品ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
87016AYLF Active PRG48 TQFP 48 C Yes Tray
87016AYLF/W Active PRG48 TQFP 48 C Yes Reel
87016AYLFT Active PRG48 TQFP 48 C Yes Reel


タイトル 他の言語 タイプ 形式 サイズ 日付
ICS87016 Datasheet Datasheet PDF 261 KB
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-845 Termination - LVCMOS Application Note PDF 62 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
PCN# : A1807-01 Gold wire to Copper Wire Product Change Notice PDF 32 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 95 KB
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 50 KB
PCN# : TB1303-01 Change of Carrier Tape for TQFP-32, TQFP-48 Product Change Notice PDF 472 KB
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview (日本語) English Overview PDF 1.83 MB
IDT Clock Distribution Overview (日本語) English Overview PDF 3.79 MB


タイトル 他の言語 タイプ 形式 サイズ 日付
87016 IBIS Model - IBIS ZIP 98 KB