The 87946I-147 is a low skew, ÷1, ÷2 LVCMOS/LVTTL Fanout Buffer. The 87946I-147 has two selectable single-ended clock inputs. The single-ended clock inputs accept LVCMOS or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased from 10 to 20 by utilizing the ability of the outputs to drive two series terminated lines.

The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The master reset input, MR/nOE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs.

The 87946I-147 is characterized at full 3.3V for input VDD, and mixed 3.3V and 2.5V for output operating supply mode. Guaranteed bank, output and part-to-part skew characteristics make the 87946I-147 ideal for those clock distribution applications demanding well defined performance and repeatability.

Features

  • Ten single-ended LVCMOS/LVTTL outputs, 7Ω typical output impedance
  • Selectable LVCMOS/LVTTL CLK0 and CLK1 inputs
  • CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL
  • Maximum input frequency: 250MHz
  • Bank skew: 30ps (maximum)
  • Output skew: 175ps (maximum)
  • Part-to-part skew: 850ps (maximum)
  • Multiple frequency skew: 200ps (maximum)
  • 3.3V core, 3.3V or 2.5V output supply modes
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Options

注文可能な製品ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
87946AYI-147LF Active PRG32 TQFP 32 I Yes Tray
Availability
87946AYI-147LF/W Active PRG32 TQFP 32 I Yes Reel
Availability
87946AYI-147LFT Active PRG32 TQFP 32 I Yes Reel
Availability

技術資料

タイトル 他の言語 タイプ 形式 サイズ 日付
データシート
87946I-147 Final Datasheet Datasheet PDF 201 KB
アプリケーションノート、ホワイトペーパー
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-845 Termination - LVCMOS Application Note PDF 62 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
PCN / PDN
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 95 KB
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 50 KB
PCN# : A1401-02 Alternate Copper Wire Assembly Site Product Change Notice PDF 36 KB
PDN# : N-12-22R2 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 363 KB
PCN# : TB1303-01 Change of Carrier Tape for TQFP-32, TQFP-48 Product Change Notice PDF 472 KB
PDN# : N-12-22R1 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 209 KB
その他資料
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview (日本語) English Overview PDF 1.83 MB
IDT Clock Distribution Overview (日本語) English Overview PDF 3.79 MB

ソフトウェア/ツール

タイトル 他の言語 タイプ 形式 サイズ 日付
87946I-147 IBIS Model - IBIS ZIP 69 KB