The 8S58035I is a high speed 2-to-6 Differential-to-LVPECL Fanout Buffer. The 8S58035I is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fiber Channel. The internally terminated differential inputs and VREF_AC pins allow other differential signal families such as LVDS, LVDS and CML to be easily interfaced to the input with minimal use of external components. The device also has a 2:1 MUX input, allowing for easy selection between two clock reference sources. The 8S58035I is packaged in a small 5mm x 5mm 32-pin VFQFN package which makes it ideal for use in space-constrained applications.


  • Six LVPECL outputs
  • INx, nINx inputs can accept the following differential input levels:
  • 50Ω internal input termination to VT
  • Two selectable differential input pairs
  • Maximum output frequency: 3.2GHz
  • Output Skew: 45ps (maximum)
  • Part-to-Part Skew: 200ps (maximum)
  • Additive phase jitter, RMS: 47fs (typical),
    (fREF = 622.08MHz, 12kHz - 20MHz, VCC = 3.3V)
  • Propagation Delay: 580ps (maximum)
  • LVPECL mode operating voltage supply range:
    VCC = 2.5V±5%, 3.3V±10%, VEE = 0V
  • -40°C to 85°C ambient operating temperature​

Product Options

注文可能な製品ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
8S58035AKILF Active NLG32P1 VFQFPN 32 I Yes Tray
8S58035AKILFT Active NLG32P1 VFQFPN 32 I Yes Reel


タイトル 他の言語 タイプ 形式 サイズ 日付
ICS8S58035I Datasheet Datasheet PDF 453 KB
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility Product Change Notice PDF 983 KB
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location Product Change Notice PDF 583 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Products for Radio Applications (日本語) English Product Brief PDF 2.34 MB
IDT Clock Generation Overview (日本語) English Overview PDF 1.83 MB
IDT Clock Distribution Overview (日本語) English Overview PDF 3.79 MB