The 8T73S1802 is a fully integrated clock fanout buffer and frequency divider. The input signal is frequency-divided and then fanned out to one differential LVPECL and one LVCMOS output. Each of the outputs can select its individual divider value from the range of ÷1, ÷2, ÷4 and ÷8. Three control inputs EN, SEL0 and SEL1 (3-level logic) are available to select the frequency dividers and the output enable/disable state. The single-ended LVCMOS output is phase-delayed by 650ps to minimize coupling of LVCMOS switching into the differential output during its signal transition.

The 8T73S1802 is optimized to deliver very low phase noise clocks. The VBB output generates a common-mode voltage reference for the differential clock input so that connecting the VBB pin to an unused input (nCLK) enables to use of single-ended input signals. The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements. The 8T73S1802 can be used with a 3.3V or a 2.5V power supply. The device is a member of the high-performance clock family from IDT.

Features

  • High-performance fanout buffer clock and fanout buffer
  • Input clock signal is distributed to one LVPECL and one LVCMOS output
  • Configurable output dividers for both LVPECL and LVCMOS outputs
  • Supports clock frequencies up to 1000MHz (LVPECL) and up to 200MHz (LVCMOS)
  • Flexible differential input supports LVPECL, LVDS and CML
  • VBB generator output supports single-ended input signal applications
  • Optimized for low phase noise
  • 650ps delay between LVCMOS and LVPECL minimizes coupling between outputs
  • Supply voltage: 3.3V or 2.5V
  • -40°C to 85°C ambient operating temperature
  • 16 VFQFN package (3mm x 3mm)

Product Options

注文可能な製品ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
8T73S1802NLGI Active NLG16P2 VFQFPN 16 I Yes Tube
Availability
8T73S1802NLGI/W Active NLG16P2 VFQFPN 16 I Yes Reel
Availability
8T73S1802NLGI8 Active NLG16P2 VFQFPN 16 I Yes Reel
Availability

技術資料

タイトル 他の言語 タイプ 形式 サイズ 日付
データシート
8T73S1802 Datasheet Datasheet PDF 931 KB
アプリケーションノート、ホワイトペーパー
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
PCN / PDN
PCN# : A1809-04 Add Alternate Assembly Location for QFN packages Product Change Notice PDF 36 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB
その他資料
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview (日本語) English Overview PDF 1.83 MB
IDT Clock Distribution Overview (日本語) English Overview PDF 3.79 MB