The IDT8T79S828-08I is a high performance, 1-to-8, differential input to universal output clock divider and fanout buffer. The device is designed for frequency-division and signal fanout of high-frequency clock signals in applications requiring four different output frequencies generated simultaneously. Each bank of two outputs has a selectable divider value of ÷1 thru ÷6 and ÷8. The
IDT8T79S828-08I is optimized for 3.3V and 2.5V supply voltages and a temperature range of -40°C to 85°C. The device is packaged in a space-saving 32 lead VFQFN package.

Features

  • Four banks of two low skew outputs
  • Selectable bank output divider values: ÷1 through ÷6 and ÷8
  • Individual outputs remain enabled while serial loading new device configurations
  • One differential PCLK, nPCLK input 
  • PCLK, nPCLK input pair can accept the following differential input levels: LVPECL, LVDS or CML levels 
  • Maximum input frequency: 1.5GHz 
  • LVCMOS control inputs
  • QXx ÷1 edge aligned to QXx ÷n edge
  • Individual output divider control via serial interface
  • Individual output enable/disable control via serial interface
  • Individual output type control, LVDS or LVPECL, via serial interface
  • 2.375V to 3.465V supply voltage operation
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Options

注文可能な製品ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
8T79S828-08NLGI Active NLG32P1 VFQFPN 32 I Yes Tray
Availability
8T79S828-08NLGI8 Active NLG32P1 VFQFPN 32 I Yes Reel
Availability

技術資料

タイトル 他の言語 タイプ 形式 サイズ 日付
データシート
IDT8T79S828-08I Datasheet Datasheet PDF 486 KB
アプリケーションノート、ホワイトペーパー
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-846 Termination - LVDS Application Note PDF 50 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
PCN / PDN
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location Product Change Notice PDF 583 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB
その他資料
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview (日本語) English Overview PDF 1.83 MB
IDT Clock Distribution Overview (日本語) English Overview PDF 3.79 MB
IDT Fanout Buffers Product Overview Product Brief PDF 739 KB
High-Performance, Low-Phase Noise Clocks Buffers product brief Product Brief PDF 378 KB