Dual 2:1,1:2 Differential-to-LVPECL/ECL Multiplexer

The 853S54I-01 is a 2:1/1:2 Multiplexer. The 2:1 Multiplexer allows one of 2 inputs to be selected onto one output pin and the 1:2 MUX switches one input to one of two outputs. This device may be useful for multiplexing multi-rate Ethernet PHYs which have 100Mbit and 1000Mbit transmit/receive pairs onto an optical SFP module which has a single transmit/receive pair. A 3RD mode allows loop back testing and allows the output of a PHY transmit pair to be routed to the PHY input pair. For examples, please refer to the Application Block diagrams on pages 2-3 of the data sheet. The 853S54I-01 is optimized for applications requiring very high performance and has a maximum operating frequency in 2.5GHz. The device is packaged in a small, 3mm x 3mm VFQFN package, making it ideal for use on space-constrained boards.

Features

  • Dual 2:1, 1:2 MUX
  • Three LVPECL output pairs
  • Three differential clock inputs can accept: LVPECL, LVDS, CML
  • Loopback test mode available
  • Maximum output frequency: 2.5GHz
  • Propagation delay: 550ps (maximum)
  • Part-to-part skew: 275ps (maximum)
  • Additive phase jitter, RMS: 27fs (typical)
  • LVPECL mode operating voltage supply range: VCC = 2.375V to 3.465V, VEE = 0V
  • ECL mode operating voltage supply range: VCC = 0V, VEE = -3.465V to -2.375V
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
853S54AKI-01LF Active NLG16P2 VFQFPN 16 I Yes Tube Availability
853S54AKI-01LFT Active NLG16P2 VFQFPN 16 I Yes Reel Availability

技術資料

タイトル 他の言語 タイプ フォーマット ファイルサイズ 日付
データシート
853S54I-01 Datasheet Datasheet PDF 318 KB Jun 19, 2017
アプリケーションノート、ホワイトペーパー
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 11, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 10, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 7, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 5, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 5, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 5, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 23, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 23, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 14, 2014
PCN / PDN
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 27, 2016
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 12, 2015
その他資料
IDT Clock Generation Overview (日本語) English Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview (日本語) English Overview PDF 3.79 MB Apr 24, 2016
ソフトウェア/ツール
853S54I-01 IBIS Model Model - IBIS ZIP 73 KB Aug 24, 2010

ソフトウェア/ツール

タイトル 他の言語 タイプ フォーマット ファイルサイズ 日付
853S54I-01 IBIS Model Model - IBIS ZIP 73 KB Aug 24, 2010