The 8714008I is Zero-Delay Buffer/Frequency Multiplier with eight differential HCSL output pairs, and uses external feedback (differential feedback input and output pairs) for "zero delay" clock regeneration. In PCI Express® and Ethernet applications, 100MHz and 125MHz are the most commonly used reference clock frequencies and each of the eight output pairs can be independently set for either 100MHz or 125MHz. With an output frequency range of 98MHz to 165MHz, the device is also suitable for use in a variety of other applications such as Fibre Channel (106.25MHz) and XAUI (156.25MHz). The M-LVDS Input/Output pair is useful in backplane applications when the reference clock can either be local (on the same board as the 8714008I) or remote via a backplane connector. In output mode, an input from a local reference clock applied to the CLK/nCLK input pins is translated to M-LVDS and driven out to the MLVDS/nMLVDS pins. In input mode, the internal M-LVDS driver is placed in Hi-Z state using the OE_MLVDS pin and MLVDS/nMLVDS pin then becomes an input (e.g. from a backplane). The 8714008I uses very low phase noise FemtoClock technology, thus making it ideal for such applications as PCI Express® Generation 1 and 2 as well as for Gigabit Ethernet, Fibre Channel, and 10 Gigabit Ethernet. It is packaged in a 56-VFQFN package (8mm x 8mm).

Features

  • Eight 0.7V differential HCSL output pairs, individually selectable for 100MHz or 125MHz for PCIe and Ethernet applications
  • One differential clock input pair CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, M-LVDS, LVHSTL, HCSL
  • One M-LVDS I/O pair (MLVDS/nMLVDS)
  • Output frequency range: 98MHz - 165MHz
  • Input frequency range: 19.6MHz - 165MHz
  • VCO range: 490MHz - 660MHz
  • PCI Express® (2.5 Gb/S) and Gen 2 (5 Gb/s) jitter compliant
  • External feedback for "zero delay" clock regeneration
  • RMS phase jitter @ 125MHz (1.875MHz – 20MHz): 0.57ps (typical)
  • Full 3.3V supply mode
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Options

注文可能な製品ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
8714008DKILF Obsolete NLG56P3 VFQFPN 56 I Yes Tray
Availability
8714008DKILFT Obsolete NLG56P3 VFQFPN 56 I Yes Reel
Availability

技術資料

タイトル 他の言語 タイプ 形式 サイズ 日付
データシート
8714008I Data Sheet Datasheet PDF 456 KB
アプリケーションノート、ホワイトペーパー
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
PCN / PDN
PDN# : CQ-16-04 QUARTER MARKET DECLINED PDN Product Discontinuation Notice PDF 560 KB
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 95 KB
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 50 KB
その他資料
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview (日本語) English Overview PDF 1.83 MB
IDT Clock Distribution Overview (日本語) English Overview PDF 3.79 MB