Low skew, low jitter PLL clock driver; 1 to 5 differential clock distribution (SSTL_18)

Features

  • Feedback pins for input to output synchronization
  • Spread Spectrum tolerant inputs
  • Auto PD when input signal is at a certain logic state

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
97ULP845AHILF Active ADG28 CABGA 28 I Yes Tray
Availability
97ULP845AHILFT Active ADG28 CABGA 28 I Yes Reel
Availability
97ULP845AHLF Active ADG28 CABGA 28 C Yes Tray
Availability
97ULP845AHLFT Active ADG28 CABGA 28 C Yes Reel
Availability

技術資料

タイトル 他の言語 タイプ フォーマット ファイルサイズ 日付
データシート
97ULP845A Datasheet Datasheet PDF 156 KB 4月 6, 2017
PCN / PDN
PDN# : CQ-14-02R2 Product Discontinuation Notice PDF 549 KB 8月 4, 2014
PDN# : CQ-14-02R1 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 545 KB 2月 10, 2014
PDN# : CQ-14-02 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 544 KB 1月 25, 2014
PCN#: A1309-03 Additional Assembly Sources Product Change Notice PDF 398 KB 10月 20, 2013