The PLL creates an error signal by dividing the VCXO clock frequency and phase by the value of feedback divider (M), and comparing it with the phase and frequency of the input clock frequency and phase, FIN, in the Phase/Frequency Detector. The output of the Phase/Frequency detector is low pass filtered by the Loop Filter to generate the Control Voltage (VC) adjustment of FOUT, thus closing the loop. When locked, the PLL output frequency (FOUT) is exactly M times the input frequency (FIN) and is phase aligned with the input reference clock. If Fout has to be equal to Fin, then a post divider of value M is added or M is set to 1. The input reference frequency, FIN, has a ± ppm tolerance due to the crystal oscillator (XO) manufacturing variations. This includes tolerance, stability, supply voltage and aging. The frequency of the VCXO has to have a guaranteed tunable range of at least the same ppm variation in order to track and maintain phase and frequency lock over the frequency variations of the input reference. Since the VCXO is itself an oscillator, its frequency is subject to the same variation due to manufacturing tolerance, stability, power supply voltage and aging. These variations must be guaranteed and should be subtracted from the total pull range. If the VCXO does not have sufficient APR and the input reference is at one of the frequency extremes, the PLL will not lock and the output frequency will not be M times the input frequency. Refer to application note AN-847 for more details. For other questions not addressed by the Knowledge Base, please submit a technical support request.