The 9DS400 is a 4-output PCIe PLL with the ability to inject spread spectrum onto the incoming differential clock, while maintaining good phase noise.

Features

  • 4- 0.7V current-mode differential output pairs
  • Supports Spread Injection mode and fanout mode
  • Two pin selectable down spread amounts: 0.5% and 0.25%
  • 50-110 MHz operation in PLL mode
  • 50-400 MHz operation in Bypass mode
  • Bypass mode
  • Supports undriven differential outputs in PD# and SRC_STOP# modes for power management
  • Output cycle-cycle jitter < 50ps
  • Output to Output skew <50ps
  • Phase jitter: PCIe Gen1 < 86ps peak to peak
  • Phase jitter: PCIe Gen2 < 3.0/3.1ps rms

Product Options

注文可能な製品ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
9DS400AGLF Obsolete PGG28 TSSOP 28 C Yes Tube
Availability
9DS400AGLFT Obsolete PGG28 TSSOP 28 C Yes Reel
Availability

技術資料

タイトル 他の言語 タイプ 形式 サイズ 日付
データシート
9DS400 Datasheet Datasheet PDF 318 KB
アプリケーションノート、ホワイトペーパー
AN-828 Termination - LVPECL Application Note PDF 229 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB
AN-843 PCI Express Reference Clock Requirements Application Note PDF 1.81 MB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB
AN-815 Understanding Jitter Units Application Note PDF 476 KB
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB
PCN / PDN
PDN# : CQ-13-03 Q2FY14 Quarter PDN for Declined Market Product Discontinuation Notice PDF 303 KB
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products Product Change Notice PDF 361 KB
その他資料
IDT Clock Distribution Overview (日本語) English Overview PDF 3.79 MB
Spread Injection PLL Clock Buffer - product flyer Flyer PDF 320 KB
Spread Injection PLL Clock Buffer - product flyer Flyer PDF 320 KB