The 9FGV1002 is a member of IDT's PhiClock™ programmable clock generator family. The 9FGV1002 provides four spread-spectrum copies of a single output frequency and two copies of the crystal reference input. Two select pins allow for hardware selection of the desired configuration, or two I²C bits all easy software selection of the desired configuration. The user may configure any one of the four OTP configurations as the default when operating in I²C mode. Four unique I²C addresses are available, allowing easy I²C access to multiple components.

Features

  • 4 programmable output pairs plus 2 – LVCMOS REF outputs
  • 1 integer, fractional or spread-spectrum output frequency per configuration
  • 10MHz–325MHz output frequency (LVDS or LP-HCSL), integer configuration
  • 10MHz–200MHz output frequency (LVCMOS), integer configuration
  • 10MHz–156.25MHz output frequency, fractional or spread spectrum configuration
  • 1.8V to 3.3V core VDD and VDDREF
  • Individual 1.8V to 3.3V VDDO for each programmable output pair
  • Supports HCSL, LVDS and LVCMOS I/O standards
  • Supports LVPECL and CML logic with easy AC coupling – see AN-891 for alternate terminations
  • 313fs rms typical phase jitter outputs at 156.25MHz (12kHz–20MHz)
  • PCIe Gen 1–4 compliant
  • Supported by IDT Timing Commander™ software

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
9FGV1002B000NBGI Active NBG24P2 VFQFPN 24 I Yes Tray
Availability
9FGV1002B000NBGI8 Active NBG24P2 VFQFPN 24 I Yes Reel
Availability
9FGV1002BQ500LTGI Active LTG24T2 VFQFPN 24 I Yes Tray
Availability
9FGV1002BQ500LTGI8 Active LTG24T2 VFQFPN 24 I Yes Reel
Availability

技術資料

タイトル 他の言語 タイプ フォーマット ファイルサイズ 日付
データシート
9FGV1002B_1002BQ Datasheet Datasheet PDF 258 KB 12月 6, 2018
9FGV1002B112NBGI Datasheet Addendum Datasheet PDF 421 KB 5月 14, 2018
アプリケーションノート、ホワイトペーパー
AN-975 Cascading PLLs Application Note PDF 128 KB 8月 2, 2017
AN-918 Programmable Clocks vs Crystal Oscillators Application Note PDF 221 KB 3月 9, 2016
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT's "Universal" Low-Power HCSL Outputs Application Note PDF 354 KB 12月 10, 2015
AN-879 Low-Power HCSL vs Traditional HCSL Application Note PDF 150 KB 4月 7, 2015
AN-843 PCI Express Reference Clock Requirements Application Note PDF 1.81 MB 5月 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB 5月 11, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB 5月 10, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB 5月 7, 2014
AN-839 RMS Phase Jitter Application Note PDF 149 KB 5月 6, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB 5月 5, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB 4月 23, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB 4月 23, 2014
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 52 KB 3月 11, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB 1月 14, 2014
その他資料
Timing Solutions Products Overview Overview PDF 4.11 MB 10月 31, 2018
IDT Products for Radio Applications (日本語) English Product Brief PDF 2.34 MB 11月 29, 2016
IDT Clock Generation Overview (日本語) English Overview PDF 1.83 MB 4月 28, 2016
IDT Clock Distribution Overview (日本語) English Overview PDF 3.79 MB 4月 24, 2016
ソフトウェア/ツール
9FGV1002B PhiClock Timing Commander Personality File v1.4 (TCv1.11.0) Software ZIP 6.09 MB 9月 28, 2018
9FGV1002 IBIS Model Model - IBIS ZIP 98 KB 5月 3, 2018

ソフトウェア/ツール

タイトル 他の言語 タイプ フォーマット ファイルサイズ 日付
9FGV1002B PhiClock Timing Commander Personality File v1.4 (TCv1.11.0) Software ZIP 6.09 MB 9月 28, 2018
9FGV1002 IBIS Model Model - IBIS ZIP 98 KB 5月 3, 2018

Evaluation Boards

Part Number Title 昇順で並び替え
EVK9FGV1002 Evaluation Kit for 9FGV1002 Programmable PhiClock™ Generator