The 8T49NS010 is a Clock Synthesizer and Fanout Buffer / Divider. When used with an external crystal, the 8T49NS010 generates high performance timing geared towards the communications and datacom markets, especially for applications demanding extremely low phase noise jitter, such as 10, 40 and 100GE.

The 8T49NS010 provides versatile frequency configurations and output formats and is optimized to deliver excellent phase noise performance. The device delivers an optimum combination of high clock frequency and low phase noise performance, combined with high power supply noise rejection.

Features

  • Ten differential outputs
  • Input operates in full differntial mode (LVPECL or LVDS) or single-ended LVCMOS mode
  • Supports output power down for power sensitive applications
  • Output frequency of 156.25 MHz, 312.5 MHz, 625 MHz or 1250 MHz
  • Sub-100 fs RMS phase noise @156.25 MHz (typical, 12 kHz - 20 MHz)
  • LVCMOS / LVTTL compatible I2C interface
  • Full 3.3 V supply voltage
  • -40 deg C to +85 deg C ambient operating temperature

Product Options

Orderable Part ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
8T49NS010-156NLGI Obsolete NLG56P5 VFQFPN 56 I Yes Tray
Availability
8T49NS010-156NLGI8 Obsolete NLG56P5 VFQFPN 56 I Yes Reel
Availability

技術資料

タイトル 他の言語 タイプ フォーマット ファイルサイズ 日付
データシート
8T49NS010 Data Sheet Datasheet PDF 711 KB 10月 19, 2015
ユーザーガイド
FemtoNG Universal Frequency Translator Ordering Product Information Guide Manual - User Reference PDF 447 KB 1月 15, 2017
Timing Solutions for Cavium Processor Designs Guide PDF 810 KB 11月 29, 2016
アプリケーションノート、ホワイトペーパー
AN-828 Termination - LVPECL Application Note PDF 229 KB 7月 5, 2016
AN-831 The Crystal Load curve Application Note PDF 308 KB 9月 22, 2014
AN-846 Termination - LVDS Application Note PDF 50 KB 5月 12, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB 5月 12, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB 5月 11, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB 5月 10, 2014
AN-803 Crystal Timing Budget and Accuracy for IDT Timing Clock Products Application Note PDF 44 KB 5月 7, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB 5月 7, 2014
AN-839 RMS Phase Jitter Application Note PDF 149 KB 5月 6, 2014
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 32 KB 5月 6, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB 5月 5, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB 5月 5, 2014
AN-837 Overdriving the Crystal Interface Application Note PDF 50 KB 5月 5, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB 5月 5, 2014
AN-832 Timing Budget and Accuracy Application Note PDF 48 KB 5月 5, 2014
AN-830 Quartz Crystal Drive Level Application Note PDF 59 KB 5月 4, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB 4月 23, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB 4月 23, 2014
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 52 KB 3月 11, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB 1月 14, 2014
AN-801 Crystal-High Drive Level Application Note PDF 109 KB 1月 14, 2014
AN-806 Power Supply Noise Rejection Application Note PDF 353 KB 1月 14, 2014
その他資料
Timing Solutions Products Overview Overview PDF 4.11 MB 10月 31, 2018
IDT Products for Radio Applications (日本語) English Product Brief PDF 2.34 MB 11月 29, 2016
Flexible Solutions for Fast Edge Rate and Low Phase Noise Requirements Overview PDF 154 KB 7月 1, 2016
IDT Clock Generation Overview (日本語) English Overview PDF 1.83 MB 4月 28, 2016
IDT Clocks for Xilinx Ultrascale FPGAs Technical Brief PDF 256 KB 4月 25, 2016
IDT Clock Distribution Overview (日本語) English Overview PDF 3.79 MB 4月 24, 2016
IDT Clocks for Altera's Stratix V and Arria V/X FPGAs Technical Brief PDF 238 KB 2月 7, 2016