This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.25V, 1.35V and 1.5V VDD operation

Features

  • DDR3-800/1066/1333/1600/1866/2133 rate
  • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs support stacked DDR3 RDIMMs
  • Phase Lock Loop clock driver for buffering one differential clock pair (CK and CK) and distributing to four differential outputs
  • Supports LVCMOS switching levels on the RESET and MIRROR inputs
  • Checks priority on DIMM-independent data inputs
  • Supports dynamic 1T/3T timing transaction and output inversion feature for improved timing performance during normal operations and MRS command pass-through
  • Supports CKE Power Down operation modes
  • Supports Quad Chip Select operation features
  • RESET input disables differential input recievers, resets all registers, and disables all output drivers except ERROUT and QnCKEn
  • Provides access to internal control words for configuring the device features and adapting in different RDIMM and system applications
  • Latch-up performance exceeds 100mA
  • ESD > 2000V per MIL-STD883, Method 3015; ESD > 200V using machine model (c = 200pF, R = 0)

Product Options

注文可能な製品ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
SSTE32882KB1AKG Active AKG176 CABGA 176 C Yes Tray
Availability
SSTE32882KB1AKG8 Active AKG176 CABGA 176 C Yes Reel
Availability

技術資料

タイトル 他の言語 タイプ 形式 サイズ 日付
データシート
SSTE32882KB1 Data Sheet Datasheet PDF 1.33 MB
PCN / PDN
PCN# : A1403-02R1 Add alternate assembly for AKG176 Product Change Notice PDF 27 KB
PCN# : A1403-02 Add alternate assembly for AKG176 Product Change Notice PDF 33 KB
その他資料
Memory Interface Products Family Overview 简体中文 Overview PDF 515 KB